Research On Low-swing Interconnect For NoC

Since the invention of integrated circuits,the goal is to make the chips work faster, lower power consumption, smaller size, integrated density greater. Along with development of IC design and manufacture process, based on bus architecture, system on chip (SoC) applications can no longer meet the requirements of on-chip data communication, so the concept of network-based computing Network-on-Chip (NoC) has been proposed and been studied extensively. But the study found that power generated by the interconnection lines and delays remain a major constraining factor in system performance, so the study for the interconnection lines become a research hotspot in academia.Interconnect dissipation power and delay are produced with the transmitted signal swing closely linked, so a low-swing signaling techniques can effectively reduce the interconnect to generate power and delay, by a large number of documents to read and summarize This article focused on analysis of eight kinds of low-swing circuit with their respective characteristics, advantages and disadvantages as well as the applicable conditions, and in SMIC0.13μm process model library, using the fourth-layer metal interconnect, width, spacing and length were 0.4μm, 0.4μm and 2mm under the conditions obtained by simulation CLC, SSDLC, SSDLC₁, SSDLC₂, PDIFF, DIFF circuit power consumption compared to CMOS the decrease in full-swing circuits are: 71%, 83%, 74%, 76% , 30%, 47%. The mj-sib, MCML circuit delay compared to CMOS the decrease in full-swing circuits are: 22%, 32%. The comparison of simulation data shows the low-swing circuit can effectively reduce the interconnect power and delay. Based on low-swing circuit analysis and simulation, this paper NoC interconnect structure system characteristics and performance requirements, select the MCML circuit as a low-swing signal drive, and double-bit sense amplifier device as a low-swing signal structure to build a low-swing each NoC Even the circuit, through the NoC simulation to be a low-swing cascade circuits to achieve data transfer rate of 1GHz, NoC verify the feasibility of low-swing interconnect circuits.