On-chip interconnect power modeling and optimization

As technology scales down quickly into submicron designs and system-on-a-chip (SoC) becomes a reality, interconnect delay saps the performance gain from faster transistors and interconnect power consumption becomes a larger percentage of the total chip power consumption. On-chip interconnect power consumption and speed performance have become important issues under these circumstances and the impact of interconnects on speed and power consumption of the overall design must be accounted for as early as possible during the design process. Careful design of interconnects is very important for power minimization and critical timing path optimization.; This thesis addresses issues concerning on-chip interconnect power modeling and architectural power optimization. A reasonably accurate behavioral level interconnect power and delay modeling method is presented and applied to a commercial chip that integrates a 16-bit DSP and a 32-bit RISC microcontroller. An architectural level simulator for the commercial chip has been enhanced to generate the bus activities for a set of signal processing benchmarks and some synthetic benchmarks. The power, delay, and energy-delay measurements for all six top level buses of the chip are reported. The largest relative error is 16% for the three benchmarks that we have the total bus power consumption data provided by the manufacture.; Different interconnect structures are designed, implemented, and simulated at the transistor level. A power analysis of interconnect structures that vary at the architecture levels and gate levels for different numbers of input ports is presented. The power simulation results show that MUXes implemented with pass transistor have the lowest power-delay product when the number of input ports is less than sixteen. However, if the input port number is thirty two, MUXes implemented with SPSD gates outperform all the other interconnect structures since SPSD gates are very fast for high fan-in circuits.; A simple bus structure may become a serious bottleneck in increasing performance and reducing the total chip power consumption. This thesis evaluates two datapath interconnection alternatives---full connection crossbars and segmented buses---at the transistor level and compares their power and delay performances against those of the simple bus structure. The results show that although a full connection crossbar consumes more energy per cycle and incurs larger delays, it consumes less energy per data transfer when the number of input/output ports is small and the crossbar operates in full parallelism. For bus input/output ports of four, eight, sixteen, the power measurements and delays are reported for both segmented buses and simple buses for 0.35 micron CMOS technology. The segmented bus power is also modeled at the behavioral level on a commercial chip. The modeling results both at the transistor level and behavioral level show that segmented buses save power and improve speed over the simple bus architecture.