Research Of High-speed Low-power Interconnect Based On NoC System

With the continuous scaling of technology and improvement of system integration, bus-based system-on-chip (SoC) encountered a series of bottlenecks, such as throughput limitation, rapidly increased power consumption and area, difficulty in global clock synchronization and expansibility limitation. To solve these problems, a new system architecture named network-on-chip (NoC) has been carried out and rapidly become a hotpot in the world wide.By reading lots of literatures, according to the structure of the NoC, several technologies used for high-speed low-power on-chip interconnection were studied. First, by adjusting the degree of multiplexing and line width-to-pitch ratio, a design method for optimizing the energy dissipation and throughput-per-unit-area is obtained. Second, the guidelines of performance such as power consumption, time delay, complexity, noise among several low-swing circuits are compared to decide the best circuit structure for a NoC system. Finally, a new driver named self-adapted driver is put forward, which adjust the driving strength in real time to make the signal delay occasionally under different dynamic crosstalk intensity, to eliminate the signal jitter, and such conclusion is verified by eye diagram simulation.