In Ulsi Chip Interconnect Parasitic Extraction And Applications

With fast advancing of semiconductor design and manufacture techniques, today's ultra-large-scale-integrated-circuits (ULSI) technology are made by very deep semimicrometer (VDSM) process. For a complicated SOC, on-chip interconnect is one of the most challenging problems. The parasitic effects of interconnects now are the bottleneck of the performance of the entire circuit system. The traditional methods of parasitic parameter extraction can't be as accurate as what they did any longer. Electromagnetic modeling and parameter extraction start playing a much more important role in IC design, and it is the foundation of the later works.This dissertation deals mainly with long interconnects in ULSI, and focuses on parasitic parameter extraction and its application in time domain analysis. It can be divided into two parts:Part 1: parasitic parameter extraction for on-chip interconnects1) Based on analytical parasitic inductance and capacitance models of on-chip interconnects, which are arranged respectively according to their relative position, a fast method to determine the bounds of parasitic inductance and capacitance is presented.2) A new inductance extraction method is presented based on the Newton-BP neural networks. At the same time, the neural network is introduced to calculate partial inductance of the multilevel interconnects; a modified-return-limited-inductance-extraction (MRLIE) method is discussed.3) Csplat is used to simulate the optical proximity effect (OPE) which could affect the interconnect. Artificial neural networks and a new concept -efficient length, is introduced into the capacitance extraction procedure for multilevel interconnect system.Part 2: time domain analysis based on RC/ RLC model of on-chip interconnects1) According to the time-domain analysis theory, delay, overshoot and crosstalk which appear on long interconnects are modeled analytically using one or two first moments of the nonlinear solution.2) Based on RLC model and n -type RLC model of the power supply trees (PST), a simultaneous switching noise (SSN) estimation method is presented. Switching-event-driven node-regroup and parameter reordering is used to turn the nonlinear noise process into linear system.