High-speed energy-efficient on-chip interconnect driver and receiver

As technology scales, on-chip interconnects become increasingly important in determining the speed and power of an integrated circuit. Signaling over on-chip interconnects has become the performance bottleneck for high-speed data communications and clock distributions.; Inverter buffers and repeaters are widely used to drive lossy on-chip interconnects because of their simplicity. However, they trade off bandwidth for latency and are energy inefficient when operating with full signal swing. Reduced-swing signaling is an effective approach to lower the power consumption on the interconnect, but at the expense of reduced speed. The pre-emphasis technique has been used to increase the interconnect bandwidth and enhance the signal integrity. However, due to the complexity of the driver, it has been largely limited to chip-to-chip communications. In order to achieve the maximum benefits without significant voltage spiking, a formal analysis is also needed to optimize the pre-emphasis waveform.; A novel signaling method is presented in this dissertation. A formal analysis is performed to obtain a closed-form expression of the driving signal to achieve an optimal waveform at the receiving end of the interconnect. Guided by this analysis, a single-ended voltage-mode driver with pre-emphasis is designed and demonstrated. The driver can operate in full-swing and reduced-swing modes. It improves the speed-power performance compared with the conventional inverter buffer. A simple reduced-swing receiver is also presented that uses high-threshold devices to avoid static power consumption and converts the incoming reduced-swing signal back to full-swing.