Automatic Layout Generation Of FPGA

To achieve the same logic function, Field-Programmable Gate Array (FPGAs)require a larger area and power than Application-Specified Integrated Circuit (ASIC).This means that FPGA has very high demand of area utilization. And manual generatedlayout has great area advantage over automatically generated layout. Therefore, most ofthe commercial FPGA layout is done by human, and the process is verytime-consuming.This paper studies how to solve the main problems of automatically FPGA layoutdesign. We focus on the island style FPGA built with SRAM-based lookup table. Themain contents are as follows:For the mainstream island style FPGA, the typical logic block and routing structureis analyzed. These logic blocks and programmable switch circuit repeat in the FPGAlogic core. To improve the performance and reduce the area and power consumption,performance of the basic circuit within the actual chip need to be carefully considered.After completing the circuit design, layout of the circuit is developed in accordance withthe flow of the standard cell development. This provides the foundation for usingstandard automatic placement and routing standard tools to generate FPGA Tile layouteven the whole FPGA layout.In order to adapt to automatic layout generation, we put forward repeated Tilestructure that can form FPGA core logic, and explore primary circuit of Tile to facilitatereplicating and abutting in the future. After determining several constraints on thecircuit and logic of Tile, replicating and abutting can possibly be done to form the entireFPGA. To simplify the layout work, FPGA architecture parameters are carefullyanalyzed and selected to improve efficiency. This paper elaborates the logical blockstructure and programmable routing structure, and determines the width of the routingchannel and design of the connection box. With the information mentioned above, wecome up with an approach to generate the netlist of Tile with structured hardwarelanguage, and complete the Tile layout using commercial backend tools.After generating Tile layout for core logic, the paper study the periphery circuit design, including the programming circuit for the configuration of SRAM cell, thecircuit can be represented by standard digital logic. Verilog hardware descriptionlanguage is used to accomplish logic implementation, and semi-custom design flowsuch as synthesis, placement and routing steps are adopted to generate layout. Thedesign of charge pump circuit to improve the transmission gate voltage is discussed.And as an analog circuit, the charge pump is laid using full-custom flow.