Research On FPGA Structure Description Method

With the development of FPGA technology and widespread of its application, the requirement of the consumers has becoming more complicated. Only a high-performance and robust device could no longer satisfy the various needs of consumers, a reliable platform, including FPGA development suites, FPGA IP cores, FPGA devices and compatible services, is only in need. The hardware description file connects all these parts within the platform, therefore a brief and accurate hardware description method plays a critical role.Many achievements have been made on FPGA hardware description methodology research in academics and industry. Most research models in academics embody only simple CB/SB and single kind of interconnect structure, which is far away behind the modern commercial FPGA architecture. On the other hand, only Xilinx Inc. has made its hardware description methodology research results to the public, while its hardware description file is way huge, which is not convenient for human reading and software parsing.Tiles in FPGA are actually copied and pieced together in FPGA hardware schematics. This paper proposes an FPGA architecture model according to the fact above. This model can be applied to heterogeneous FPGAs and for various interconnecting architectures. Also based on the model, this paper defines a set of complete and detailed grammatical rules to describe the FPGA architecture. Experimental results show that the description method can not only delineate FPGA hardware information but also work correctly with FPGA software system. Compared with VPR6.0the way we describe FPGA chips can be utilized to describe various interconnect structures. The description file is much smaller in size than the Xilinx counterpart (1.1%of the Xilinx counterpart when used to describe Virtex-Ⅱ chip with the gate size of three million gates, thus making manual inspection and software parsing easier.