Fpga Evaluation System Layout Module Design

It's very useful to put FPGA IP core into SOC chip. But it's difficult to design an FPGA architecture which is suitable for application domain circuits and make the system work perfectly.We try to find out the exact FPGA IP core for the application domain circuits. So, the FPGA evaluation system comes into being to find the most suitable FPGA architecture based on the specified domain circuits.The flexibility of FPGA structures brings new challenges to the FPGA evaluation system. Different from the commercial software systems, the FPGA evaluation system have to model all kinds of FPGA architectures in different sizes and different structures. To get the fair evaluation results, the FPGA evaluation system should adopt the algorithm which is irrelated to any FPGA architectures so as to get fair evaluation results. Based on the rule of universal and fair standard, the frame of the FPGA evaluation system was built.With the modeling of all the FPGA architectures, the model of the universal placement and routing software VPR was expanded to flexibly support the different sizes and architectures of FPGA. A more complete modeling method was developed to describe different FPGAs. The users can find the best routing architectures by our universal placement and routing module. The test shows that our module can describe the commercial FPGA architectures detailedly.To deal with the hierarchical FPGA architectures, a modified partitioning algorithm was introduced here according to special hierarchical FPGA model based on the previous works. The algorithm combines the simulated annealing algorithm with the ratio-cut idea to ascertain the level of the multi-level multi-way partitioning and considers the number of cut lines while partitions CLB into cluster, then performs a k-way optimization without changing the level, so as to achieve a better partition result and improve the usage in HFPGA, then optimize the FPGA performance.Meanwhile, the FPGA macro block placement is introduced here based on the floorplanning problems. With the reasonable cost function and solution, the FPGA floorplanning problems are settled pretty well. We propose a method to describe the routing resource in FPGA macro block. The results are satisfying and they show that the placement and routing step with the FPGA macro block can be done by our method.What's more, an EDIF compiler is introduced here. The results show that the EDIF compiler works normally.