Design And FPGA Verification For The MDIO Interface Logic Integrated Circuit

With the large development of Integrated Circuit technology, the chip's scale is getting larger and larger. Integrity and frequency are getting higher and higher. But the design ability faces a big challenge. The IP reuse is the most effective method to solve the problem that the chip design is faced with.MDIO interface module block is an interface that is used in MAC level to control and manage PHY devices.With the rapid development of Ethernet technology and the MAC to be used more widely, the MDIO interface also has more applications. So it is very important for many kinds of designs of Ethernet Interface chip to design the MIDO interface to a reuseable IP core.The design of the MDIO interface is described in detail in this thesis. Firstly every sub module's specification and design method are intrduced, and then the simulation results of RTL level are demonstrated. At last the MDIO interface is verified by FPGA and the function and performance reach the required standard. Now as an IP core the MDIO interface is used in the chip of Ethernet Interface successfully.