OPC Optimization Design Method Based On Nanoscale Technology Standard Cells

Over the past several tens of years, improvements to lithography have brought devices sizes down from above lum to below22nm design rules. Aggressive scaling of CMOS devices has pushed IC manufacturing to the extreme, so that the problems and difficulties encountered during fabrication can no longer be addressed by manufacturing process alone. Lithography and stress variation are two dominant effects that significantly impact the functionality and performances of circuit designs. Moreover, the fabrication variations at advanced IC techno logies are highly dependent on the physical layout IC manufacturers nowadays rely heavily on resolution enhancement techniques (RET), such as OPC, SRAFs, PSM to modify the chip mask database (GDSII) and achieve better printability, higher yield, and less variability.In this dissertation, we focus on OPC. OPC is used in lithography to increase the achievable resolution and pattern transfer fidelity for IC manufacturing. The fundamental idea behind OPC is to modify the mask itself in order to correct for non-idealities that occur during pattern transfer.As critical dimensions of integrated circuit continue to scale down, especially at90nm technology node and beyond, model based optical proximity correction (OPC) has become necessary. However, the rapid reduction in critical dimension of integrated circuits has lead to substantial mask data expansion and prohibitive runtime for mask design based on traditional model-based full-chip OPC. This has added to the total cost of IC manufacturing and become an increasingly critical issue optical lithography.In this paper, we propose a new kind of cell wise OPC which pre-optimize the layout of the standard cells. When compared to conventional OPC approach, the proposed cell wise OPC achieved11%reduction in mask size of the standard library layout and up to15.03%reduction in run time for the library OPC. The proposed approach is validated via simulation using40-nm foundry libraries and ISCAS’85/89benchmark circuit. The performance(timing, area and power) of the circuits which use the optimized libraries can meet the design requirements. The method proposed in this dissertation is feasible.