Design For Manufacturability Of Deep Sub-micron Standard Cell

With the size of IC becoming larger, ASIC develops faster due to the short development cycle, low development cost and high reliability. Good functional standard cell library is a bridge to link ASIC users and process line. It is impossible to have high level ASIC design without good standard cell.Now VDSM(Very Deep Sub-micron) era has come in IC design and manufacture field. Beginning from 0.18μm technology node, Sub-wavelength Lithography is widely used in semiconductor manufacture process. When the IC character is very close to the limitation of exposure system in theory, the real shapes created on the wafer will be seriously different from the layout. The distortion may influence functionality and performance of IC products and lower the production yield. What's more, with the Sub-Wavelength Lithography continues extending to its physical limit, new kinds of problems of IC manufacturability and yield keep emerging.New physical design rules are implemented in Sub-Wavelength Lithography circumstance to solve the DFM (Design for manufacturability) problems in standard cell design. New physical design rules which are evaluated by EPE (Edge-Placement Errors) and the area of the cell, are proved to have better performance in manufacturability and yield on the beginning of IC design process. Based on the new design rules which will shorten design periods and win competition in the market, a set of DFM-friendly 0.18μm standard cell layout are designed.