The Study And Implementation Of Clock Structure For Fishbone

Nowadays, the capability of high-speed data transferring and processing is a basicrequirement for a modern high-performance processor. As the vector for the clocksignal transferring of the processor, the structure of the clock tree determines theperformance of the whole processor. So the selection and design of the clock treestructure becomes very important. The balanced tree is an usually used clock structure.But it is with the features such as considerable latency, skew and OCV, which are thedirect factors causing the processor’s low performance or being down. So the design ofthe clock structure with low latency, skew and OCV becomes one of the criticaltechnologies in the design of high-performance processor.There are mainly two clock structures, namely, tree structure and mesh structure.The design based on tree structure is relatively mature technology, and it can be realizedautomatically by EDA tools. So it is commonly used in the clock design of integratedcircuit. By contrast, the mesh structure can be only realized manually, though it can wellmeet the performance indexes required by the high performance processor.Based on the relevant researches at home and abroad, this thesis is focusing on thestructure and design realization of the high performance processor under the nanometertechnology. With the thorough research on the fishbone clock structure, the main workand innovations of the thesis includes:1. In order to support the analysis and research on the circuit level, a circuit modelfor FB is built with the combination of Π model and distributed RC model. And theanalysis on the accuracy of interconnection delay model is done.2. According to the fishbone clock structure, the built circuit model is simulated inSPICE after all parameters are set, and then all the generated indexes are analyzed andpre-estimated. The simulation results show that this model conforms to the realized FBclock network with an accuracy of more than95%.3. To realize the mesh structure automatically by EDA tools, a whole set ofalgorithms and tools are developed. The efficiency of the mesh clock structure’srealization is improved greatly.Combining with the advantages of both mesh structure and balanced tree structure,a hybrid clock structure (fishbone-balance-tree, FBT) is realized. The FBT network,which improves the performance of the processor further, can not only achieve the lowclock latency and skew, but also realize the useful skew in critical paths.