The Design Of Digital Receiver Based On FPGA

The concept of software defined radio has been widely used in the communicationand radar systems. Compare with the traditional hardware based radio devices, it has theadvantages of programmable logic, digitalization, velocity. The software defined radioaimed to use normal programmable logic deceive or DSP as hardware platform andachieve the wireless function based on software.The performance of the receiver will directly affect the whole system operation anddecide whether it is reliable and practical. FPGA+DSP architecture is popular in thesoftware defined radio digital receiver, the digital signal from A/D will be processedthrough FPGA to achieve interface and digital down converter function, thentransmite to DSP to do the complex signal operation.In this paper Digital Down Converter (DDC) was mainly discussed as one of thekey technology in the digital receiver. High bit-rate digital signal can be transformed tolow bit-rate digital signal with DDC technology, so it can be processed by DSP inreal-time. Although there are some DDC chip for people to use, but they lack flexibilityand most of them are expensive. As the FPGA device’s performance growing strongerand the costs reducing, it is practical and efficient to design DDC based on FPGA.The application of digital receiver was discussed in this task. First, the basic theoryof software defined radio in radar system was discussed in this paper. Then analyse thetheory of each section of DDC and show the design method base on FPGA. And checkthe result though Modelsim6.5. At last, Compare the design result with the ideal resultwhich is generated by Matlab software to verify whether the design has achieved thesystem requirements.