Research Of Software Defined Radio IF Digital Receiver Based On FPGA

As software defined radio (SDR) theory has increasingly matured and completed, SDR technology has been widely used in contemporary military and telecommunication areas. Recently, Digital IF technology has made rapid progress in SDR technologies. IF digitized receiver based on SDR has been become one of the most important parts of modern radar, telecommunication and measure-control systems. Therefore, it is very significant to research the technology of IF digitized receiver.With the rapid growth of programmable logic devices in density, size and speed, FPGA (Field Programmable Gate Array) reveals incomparable superiority in competency, cost, power and flexibility. Using FPGA to design electronic circuit is a hot spot of research currently, and it will become the future development trend of design.This thesis focuses on the study of designing the IF digital receiver based on FPGA. Based on SDR common models of modulation and demodulation, this thesis presents the overall program of SDR-based IF digital receiver system. In the end, the design of IF digital receiver based on FPGA has been implemented using the tools of Matlab, ISE and ModelSim.The main research work in this thesis can be summarized as follows:Firstly, aimed at the shortcomings of look-up table method for the realization of NCO (Numerical Controlled Oscillator), this thesis focuses on the study of CORDIC (Coordinate Rotation Numerical) algorithm. Using this algorithm, not only the design of NCO can be achieved, but the mixing operation, between IF digitized signal and local oscillator digital signal, can also be completed. Thereby, an efficient way to implement down-conversion without multipliers can be obtained in this thesis. In addition, the structure of the full pipeline implementation is adopted in this thesis, and the module's maximum frequency is improved.Secondly, analyze the principle of efficient decimation filtering of the CIC (Cascaded Integrator Comb) filter, discuss the parameters affecting the performance of CIC filter, design five-stage CIC filter, and effectively implement the sampling rate conversion.Thirdly, the principle of HB (Half-Band) filter has been introduced and analyzed. According to the target, single-stage HB filter has been designed to achieve the reduction in the sampling rate by factor 2. Fourthly, analyze the principle that the raised cosine filter can be used to implement transmission without inter-symbol interference. Design the root raised cosine filter, which is matched with the sending filter.Fifthly, design the sampling decisions and parallel-serial conversion modules. In the end, implement the demodulated output of base-band signal and the function of IF digital receiver.