Design Of24Bits96KSPS Sigma-Delta Modulator

With the wide application of high-resolution ADC in the fields of communicationand multimedia, oversampling Sigma-Delta ADC become one of the focus. Sigma-DeltaADC is composed mainly by the two parts of the Sigma-Delta modulator anddown-sampling digital filter. Sigma-Delta modulator using oversampling and noiseshaping, can effectively reduce quantization noise, improve the signal-to-noise ratio.Digital filter using the down-sampling digital filter technology, can filter out the highfrequency quantization noise, to reduce the sampling frequency. Compared with theNyquist ADC, Sigma-Delta ADC can simplify circuit design, reduce the requirements ofthe unit circuit performance and component accuracy and reduce production costs.Through the study of the Sigma-Delta ADC theory, based on the the SMIC65nm2.5V/1.2V CMOS process, using6.144M sampling rate and64times oversampling rate,a24-bit96KSPS Sigma-Delta modulation with16effective bits is designed. The CIFFthird-order (2-1) cascaded MASH modulator structure is used by Sigma-Deltamodulator. System-level design of Sigma-Delta Modulator is finished by Simulink.Taking into account the impact of the non-ideality factor of Sigma-Delta modulator, thecircuit simulation is finished with Hspice. Overall circuit includes a buffer circuit of thefront end of the modulator, the current reference circuit, the integrator comparatorcircuit and a two-phase non-overlapping clock circuit. And on the basis of simulationdesign of the overall circuit complete the layout of the entire circuit.The overall circuit simulation results show that the signal-to-noise ratio of the24bits96KSPS Sigma-Delta modulator is102.9dB, the significant bit is16.8bits, thelayout area is1098μm×612μm, to meet the system requirements of high accuracy.