| With the rapid spread of wireless communication technology in recent years,the Sigma Delta ADC with low circuit power consumption and large signal bandwidth has been the focus in the research of analog-to-digital convertors.And,the continuous time Sigma Delta modulator has many advantages,such as good inherent antialiasing characteristics and low requirements for slew rate in operational amplifier.Compared with discrete-time Sigma Delta modulators,the continuous-time ones can operate at higher signal sampling rate,leading to a large bandwidth.Based on the aforementioned theories,a 11 bit continuous time Sigma Delta modulator with 10 MHz signal bandwidth is proposed in this paper according to the application background in the high speed communication systems.In order to compare the performance of modulators between different quantizers,this paper adopts a three-order modulator structure which combines a Flash ADC with a TDC.In this work,according to the circuit design index,the loop filter function and the noise transfer function are synthesized by SDToolbox in MATLAB,and compared with the designed Sigma Delta mathematical topology.After the pulse constant transformation and coefficient scaling,the approximate range of the resistance and capacitance in the modulator are figured out,and the loop filter function of mathematical topology is mapped to the circuits.In the proposed modulator structure with Flash quantization,the power efficiency operation amplifier which applies the feed-forward structure is adopted in the integrator.And the high-rate current rudder is employed in the feedback DAC structure.Besides,the NRZ feedback waveform is established to curb the sensitivity of the modulator to the clock jitter,and a half-cycle delay and a zero-order compensation loop are introduced to eliminate the effect of loop delay on modulator performance.In order to suppress the effect of DAC nonlinearity on the direct noise-added of the modulator,the Flash quantizer is followed by the DWA circuit module,then the average selection times of the quantizer output for each current steering unit is nearly equal in unit time.Moreover,the white noise introduced by the mismatch of the actual DAC current steering is diminished by the first-order noise shaping to improve the overall performance of the modulator.In this paper,the Flash quantized modulator,implemented in TSMC 65 nm process,can work at 320MHz sampling rate under 1.2 V supply.And the simulation results show that,under the target signal bandwidth of 10 MHz,it achieve a 78.5 d B peak SNDR and a 12.75 bit ENOB,and draws 15 m W power.The TDC quantized modulator structure applied in this paper replaces a 4 bit Flash quantizer and a current steering feedback DAC by a pulse width modulation(PWM)generator and a time-to-digital converter(TDC).Compared to the Flash quantized modulator,the TDC quantized which adopts single-bit feedback is immune to the noise introduced by the nonlinearity of the multi-bit DAC,and in turn the design of the dynamic cell matching circuit module is omitted.In this paper,the overall design of TDC quantized modulator is completed by TSMC 65 nm.And the sampling rate is 250 MHz at 1.2 V supply.The simulation results show that the peak SNDR is 72.9 d B,and the ENOB is 11.82 bit,and power consumption is 11.5 m W at the target signal bandwidth of 10 MHz.Finally,the research on the decimation filter is followed.In this paper,the structure of whole digital decimation filter consists of the CIC filter,CIC compensation filter and half-band filter by the way of cascading,then the high-frequency noise of the modulator can be filtered and a 16-fold factor of reduction can be achieved.Besides,the CIC filter is placed in the first stage to achieve 8 times down sampling because of the achievement of a large decimation factor and the good anti-aliasing characteristics,the second stage is the CIC compensation filter due to its compensation performance for the pass band roll-off of the CIC filter,the third stage employs the half-band filter to achieve the last 2 times extraction.In this design,the simulation is first performed in MATLAB,and the Verilog code of the digital decimation filter is verified by Model Sim for functional simulation,then the final output is subjected to DFT analysis.The simulation results show that the input signal sampling frequency of the digital decimation filter is 320 MHz.After decimation,the output signal sampling frequency is 20 MHz,and the transition band bandwidth is 200 KHz,the pass band ripple is less than 0.1 d B,and the ENOB is 12.88 bit.All the performance indexes meet the design requirements. |
