Reseach And Design Of B Code Synchronization Technology Based On SOPC

This paper mainly discusses the theory of "time unified system" and the method, as wellas the key technology to realize it. From the point of view of project implementation, itexpounds the design of hardware and software in detail by the application of IRIG-B code(hereinafter referred to as B yards) to realize time unified system.This system is considered as a complete set of electronic equipment which can realize theunification of time and frequency of the whole experiment by providing standard time andfrequency signal for conventional weapons test, missiles and space test."Time unifiedsystem" was first introduced in the range and it is the time standard for the collaborativeworking in the whole range, to achieve time synchronization of all the measuring devices. Butwith the development of science and technology, more and more projects, such as moderncommunications, navigation, power dispatch, astronomy, land measurement, earthquake andtransportation engineering, and scientific research field also present a high demand for highprecision time synchronization.In this paper, by the comparison of various clock ways and advantages of differentprocessors at the first beginning, the GPS clock way has been selected. Through C8051F340,the SOC singlechip, to obtain the standard time information of the GPS receiver and realizeits IRIG-B encoding, completing the design of the source code in system B; secondly,through the field programmable gate array (FPGA) and the application of SOPC technologyin its platform to finish the design of the time unified system terminal, realizing thedemodulation of code B and the transmission from time information to user device, thuscompleting the overall design of the time unified system. In the encoding part of this paper,through the selection of the GPS clock way and the singlechip local time to achieve theabsolute time synchronization and relative time synchronization of the time unifiedequipment. The production of code B is verified by the Protues singlechip software, and itis convenient and effective to test the feasibility of design, realizing the software design ofcode B production. The decoding part in the FPGA employs a combination of methods:“hardreal-time part+Nios Ⅱ soft-core+logic circuit”, namely, the SOPC technology to completethe code B demodulation and the communication of the time unified system terminal. In addition, to meet the various frequencies of different user equipments, the time unifiedsystem outputs synchronizing signal of various frequencies for the users to choose.Compared with the previous design methods, the application of SOPC technology makes thesystem more integrated and flexible. At the same time, it simplifies the design of the interfaceof the time unified system terminal, making it easier for the system to upgrade, modify andexpand.This paper has finished the achievement of standard time information for the GPSreceiver, the IRIG-B encoding and decoding of the time information, the generation ofsynchronization pulse signal and the serial output of the decoding time information, realizingthe overall design of the time unified system. Through the software of Proteus and QuartusⅡ, the encoding and decoding has been verified and tested in the hardware platform.According to the result, the synchronization time of the system has a high level of precision,reaching the expected design goal.