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Research And Design Of IRIG-B Code Timing System Based On PCI-E

Posted on:2015-04-15Degree:MasterType:Thesis
Country:ChinaCandidate:B TangFull Text:PDF
GTID:2298330431491391Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
Timing terminal is a specialized electronic device which provides reference time and frequency information to the test system in TT&C station, and it is widely used in communication、measurement and other fields. Through the research of time synchronization of IRIG-B code、data transfer of PCI Express bus and some others technologies, this paper designs and develops a IRIG-B code time terminal system based on PCI Express bus. Not only does this system provides high precision time synchronization signal, but also interact data with host computer. And it can be used in measurement and control system such as computer and other equipments.Through the brief description of time synchronization technology、PCI Express bus technology and satellite navigation technology, and combined with the performance requirement of system, this paper proposes the overall design scheme. In the hardware circuit design, in order to solve the problems of BD/GPS dual-mode interface、input signal processing of IRIG-B code、output signal decoding of IRIG-B、 the complication of data transfer and so on, this paper uses some advanced chip for circuit design, such as using CH367to simplify the bridge of PCI Express bus. Aiming at the signal function of terminal equipment、the precision and stability of time code、 the software design of application layer and other problems, this system provides two methods, such as the logic design of BD/GPS dual-mode switching、the coding and decoding of IRIG-B code. Be based on the user’s own needs, the former can send commands to the satellite through host computer and provide time information for B code. The latter can decode IRIG-B code for some new methods such as "a standard test method". In order to send the decoding time or satellite time to host computer through bus, this paper uses IP core which from FPGA to generate a RAM virtual memory for data cache, and then combines CH367with VC++to design application interface to satisfy time display.The experimental results show that:The system can switch the mode of the satellite smoothly, the generated IRIG-B code not only can meet the performance but also has strong drive capability, and in the data transmission of PCI Express, the time information can be correct display in the application interface. Above all, the system has advantages of simple structure and convenient operation.
Keywords/Search Tags:PCI Express bus, dual-mode switch, FPGA, IRIG-B code, Atmegal6L
PDF Full Text Request
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