Design Of Time Synchronization System Based On IRIG-B Code Demodulation Technology

The accuracy of time synchronization,to a large extent,determines the performance of the navigation,positioning and timing process.In addition,the high speed and large capacity information transfer and fusion between different navigation systems are very strict on the time synchronization in the integrated navigation system.Time and frequency standard is one of the most important factors affecting the accuracy of time synchronization.Phase-locked loop,as a kind of phase tracking and locking technology,is an important part of the generation and maintenance of standard time frequency.This paper is design to calibrate the local clock,and improve the local clock stability based on phase-locked loop,which is able to tracking phase.Firstly,this paper analysis the principle of the IRIG-B timing technology and method of IRIG-B demodulator,then,establish the method of generating the standard second pulse by decoding the IRIG-B code.In this situation,the paper complete software design of IRIG-B code demodulator.Secondly,a mathematical model of the phase locked loop is modeled and analyzed in detail under comprehensive analysis on it.Loop filter is the most important part of the whole phase locked loop technology.This paper focuses on the design of the phase locked loop filter,then design and discrete loop filter based on Winner linear filter theory and bilinear transformation theory.Besides direct digital frequency synthesis technology and phase-locked loop technology are adopted to achieve synchronization between local second pulse and standard second pulse.Finally,the paper completed the simulation on development software of the field programmable gate array for the designation.After that,the paper completed the design,fabrication and debugging of the circuit board.Then,this designation was downloaded to the field programmable gate array.It comes out that this design can demodulate the IRIG-B and tracking phase difference well and truly.It was proved that the design is correct,and the results are quite good through hardware verification.