Design Of IRIG-B Code Decoding Based On FPGA Technology

Time information is a very important physical parameter. With the development of modern science and technology, including communication, power transmission, navigation and weapon test are asking for high-precision time service or time correcting. It always takes a high-precision timing signal as a sign or for reference. IRIG-B timing code (B code for short) is a international common criterion. The B code as a time servicing could totally satisfy the requirement of underwater acoustic experiment.In recent years, field programmable gate array (FPGA for short) has been developed rapidly, which has a strong real time parallel processing ability. In the paper, FPGA is used as a core processor part. The paper has realized the hardware design and debug of the real time B code decoding system which is based on FPGA technology.Firstly, the paper introduced the concept of the B code. The important part is the format and standard interface of B code. The paper does a research in features and standard parameters of both the direct current (DC) B code and alternating current (AC) B code. By the software simulation, paper simulates the process of the generation and decoding of B code. Paper does a lot work on how to realize the decoding based on FPGA technology, which including the respective decoding methods of DC code and AC code, and the lpps signal generation. By picking up the chip types of A/D convert module, FPGA, communication module and interface level conversion module, paper completed the work of hardware design of B code decoding system. Paper also designed the schematic and made the PCB board. After the welding and debugging, paper analyzed the result of the test, and gave out the advises of promotion.According to the test result of the PCB board, the hardware design of the B code decoding system reached the requirement, and achieved the expected goals.