The Fpga Interconnect Resources Assessment And Design

Filed programmable gate array, FPGA, can reduce the risk, the cost and the time-to-market and, therefore, is wildely used in electronic systems. With FPGA’s increasing array size, and the logic resources’ becoming heterogeneous, the interconnection resources, which take the biggest part in power consumption, area and delays, are becoming complicated. How to design FPGA’s interconnection resources reasonably and efficiently is an important problem.Starting from the routing issue, this thesis analyzes the routers’ algorithms and researches the relationship between the size of the minimum loop in the routing-resources graph and the flexibility of the signal transmission in the routing resources. And then this thesis propose an evaluation method based on the minimum loop size in the routing-resources graph and the algorithms to get the minimum loop size in directed or undirected graphs.After that, a novel method that maximizes the minimum loop size in the routing-resources graph is proposed according to the new evaluation method. Thus this thesis design a new switch box, called MLM switch box, and a process to generate detailed connections of a GRM from parameterized FPGA interconnection description.Experimental results show that while compared with 4 typical academic switch boxes model, Disjoint, Universal, Wilton and JSB, MLM is at average level in timing and outperform all of them in routability by 17.7%,8.0%,2.4% and 2.2% separately.