Design And Verification Of SoC Interconnection Architecture Based On AXI

With the development of integrated circuit and semiconductor technology, the design of system on chip(SoC) based on IP core reuse technology is more and more widely used in various fields. In view of the interconnection of IP cores in SoC, the traditional bus architecture shows low transmission bandwidth, hard to support parallel communication, limited address space and other issues; IP core communction protocol also reflects many shortcomings, such as difficult to achieve low latency,high frequency,low power consumption and flexibility. In this paper, the SoC matrix interconnection architecture based on AXI not only reflects the advantages of AXI protocol, for example achieving low latency, high efficiency,high throughput transmission in point to point mode, but also avoids some shortcomings of the bus architecture, realizes N-M parallel communction. Article verifies the function of the design. The main work of this thesis is as follows:1. Analyse the transmission process and architecture features of AXI protocol,and combining the requirement of parallel communication in system, design a topological structure that is multi-data caches for master and shared address buffer,multi-data caches for slave, with which realizes outstanding transfer, out of order access and N-M parallel communication based on AXI protocol between IP cores and interconnection module.2. Design a arbitration configuration register, that can be written by handshake protocol, with which SoC can realize more efficient communication in different occasions by the arbitration priority.3. Design a SRAM controller with AXI interface and AXI2 APB Bridge, both can suspend AXI interconnnect architecture as slaves. Realize burst write transmission in which there is no difference about the order of data and address. Make optimization of these modules.4. Build UVM verification platform to verify the function of modules and compoments, write the driver, monitor, sequencer, agent, reference model, scoreboard and other components in UVM platform, generate constrained random stimulus, and check the results automatically, use different testcases to verify different functional points, and the result is correct.