A Research On The Analysis And Implementation Of Pipeline FFT Architecture Resources

The advancements in digital systems have revolutionized our way of living.. This ismainly due to the advances in digital systems, which are slowly and gradually replacing the oldanalog systems. Nowadays, digital systems are prepared to face the requirements of the mostdemanding signal processing applications, which set strong conditions in terms of clockfrequency, throughput, power consumption, latency and real time computation. In order to meetthese strong requirements it is often necessary to resort to hardware devices such as ASICs(Application Specific Integrated Circuits) or FPGAs (Field Programmable Gate Arrays).Thusthese devices permit to achieve a very high performance in the computation of signalprocessing algorithms.However the hardware world differs from the algorithmic transformations e.g. amathematical simplification of an algorithm does not necessarily lead to a simpler circuit.Further an algorithm may have different hardware implementations based on the desiredrequirements such as latency and throughput. The pipelined architecture is often preferredbecause they provide high signal processing capabilities as well as reasonably low hardwarerequirements. Besides, efficiency not only includes the selection of a certain kind ofarchitecture but also the optimization of the selected type is desired. Indeed hardware is used indemanding applications for maximizing performance or reducing power consumption, so thearchitecture must be optimized in order to achieve these goals.This thesis investigates the best possible implementation of FFT architecture on FPGA.SDF architecture is considered because it fulfills the requirement of most of the communicationarchitecture. By paying special attention to how the design efficiently can be mapped to thecourse grained hardware structure of a target FPGA, better implementation results can be obtained. This is illustrated by mapping a R2SDF FFT processor that has been targetedtowards both Virtex-4and Virtex-6devices. The FPGA-mapping of this design have beenexplored in detail. Algorithmic transformations that allow a better mapping are proposed,resulting in implementation achievements that are better than earlier published work.In addition, different equivalent algorithms of radix22having the same implementationcomplexity but with possibly less switching activity memory complexity between subsequenttwiddle factor coefficients and index mapping were simulated. Further alternatives of rotatorswere also compared to see which utilizes the least number of adders for a particular rotationangle. Selecting algorithms having lesser switching activity and memory complexity propertiesof the twiddle factor resulted in savings in power consumption and area requirement.