FPGA Implementation Of The Switching Module For A Large Capacity ATM Switch

ATM technology uses fixed-length packet to implement the asynchronous time division multiplexing and switching of high-speed hardware. It has a lot of advantages, such as guaranteeing the quality of service for the real-time services and good flow control, and has obvious superiority in the space switching and private network. Therefore, in order to master the core technique of communication networks and own the intellectual property rights it is very necessary to study the design and implementation of the ATM switching based on FPGA.Sponsored by the project named prototype of the 10Gbps large capacity ATM switching on-board, this dissertation summarizes the issues of the ATM switching structure and buffering structure. It also investigates the design skills of FPGA, the effects and principles of the static timing analysis (STA), and concludes the methods in diverse aspects for improving the FPGA design performance. On the basis of the implementation scheme made by whole project group, this dissertation focuses on two issues. The first is the design and implementation of switching module’s sub-module in VHDL language, including the sub-module of cell receiving/sending, bus width transformation, cell storing in/reading out schedule, control of cell priority and flow; The second issue is the software design and simulation for all the modules mentioned above. The hardware test of the prototype switch has validated the correctness of the switching module designed. Finally, the issues to be studied further are also proposed in the dissertation. The work made in this dissertation lays a good technical foundation for developing the homemade chips of ATM switching.