The Research Of Serial Physical Layer Of High Speed Serial Bus Based On Programmable Chip

Along with the much desire to embedded systems for people, I/O interconnection architecture and system network is the key factors that impact the I/O performance. Traditional PCI bus could not satisfy the requirement of real-time transaction, rich function and flexible system topology. RapidIO is chases this trend.and it is a high speed data rate, high efficiency for the transmission, low consumption, more types and no restriction to the system topology, it has became the leader in the interconnection of the embeded systems.This dissertation's main content is as flows:①Make a choice between the VHDL and Verilog which according to the IEEE standard; Make a choice from many programmable chips with their cost and resources.It provides a referenced platform for the following designers.②Partition the design into some sub modules based on the research to the bus Specification.. Decide the sub modules'function and implement modes to make sure that the sub modules can be implementing and their complexity is appropriate. It gets some good results that reduce the complexity of the design and sizes on a less resources of the chips.③Coding the modules based their function and modes. The finite state machine, the physical code sub-layer's 8B/10B encoder and decoder and the transceiver are the key modules.It is appropriate to fit the modules on the programmable chips.④Analyze the result which has been finished. It contains three sections: clock frequency, resources used and power consumer. They are the most aspects for all. At last, compare with the PCI bus in some aspects, because the PCI bus is the most important bus in the past several years. The result proves that we can use some less resource to implement some higher efficiency bus.