Design And Implementation Of SATA Adapter Using FPGA

Serial ATA (SATA) is a high speed serial bus. It has point to point transfer mode, embedded data and commands checking unit, support hot plug and play, the band wide is 150MB per second (SATA version 1.0) or 300MB/s (SATA version 2.0). The product of SATA is widely used, but the entire products are provided from abroad, no chips developed on an independent basis. In the Embedded area, no SATA chip being provided right now.Analyzed SATA protocol, developed a stack layer model of SATA adapter, the stack model contains a host interface layer, an ATA simulation layer, a transport layer, a link layer and a physical layer. Asynchronous FIFO is arranged to communicate between the layers. Implement multiple state machine cooperation design. Designed high speeds parallel CRC encode decode unit, and parallel 8b to 10b encoder/decoder, and scrambling unit using line feedback shift register. Implement 1.5Gbps differential serial signal communications channel. Implement 133MHz max speed PCI host interface, 32/64 parametric bus width, with address configuration space and DMA. Analyzed and tested the depth and performance of FIFO, calculated the FIFO depth's affection to parallel degree of the stack layer. Tested the performance of SATA Adapter, the working performance is as good as commercial product. Write simulation verification script, it make the RTL code work correctly. Gives an IC design automation model, use a new description strategy, it can translate the design task to synthetic HDL code, and can be used to a wide classic of chips.