The Design Of Radar Signal Acquisition System

Radar signal acquisition system, as the VTS (Vessel Traffic Management System) sub-module is the core unit of VTS system, it is the core technology of VTS system. People with technological innovations of the data processing speed and quality of a higher demand, the front end as the data processing system, acquisition system directly affects the speed and accuracy of the data processing system speed and accuracy.Against the background of this problem proposed a dual FPGA+PCI system configuration, two different division FPGA, FPGA is responsible for the first sheet A/D converter converts the digital signal from the acquisition management, and overall system timing control logic; second sheet FPGA is used to preprocess the radar signal, the external data in the SDRAM memory depth can bring guaranteed, and can meet the requirements of processing speed algorithm. Data transmission interface restricts the acquisition system performance characteristics, PCI bus data transfer using a parallel structure, the transfer rate of up to hundreds of megabytes on the transmission rate can meet the system requirements.Focus of this study is divided into hardware and software components, the hardware part of the whole collection system implemented on the basis of existing analog capture card in another digital circuits, electromagnetic compatibility therefore capture card acquisition system hardware research question is the most important issue, radar acquisition card interface circuit is the forefront of the hardware circuit, because the radar of the original signal parameters (such as amplitude, polarity, offset, etc.) often can not meet the requirements of ADC and FPGA, so be on the radar of the four signals (video signal, the trigger signal, the signal azimuth, true north signal) conditioning, A/D conversion circuit can capture card80MHz sampling rate, to ensure their normal stable work is to study the hardware part of the main problems; software part the focus of the internal FPGA system design, including the data cache management, and FPGA for SDRAM, PCI9054read and write control. Finally, this paper briefly describes the format based on WDM driver development process, through DriverStudio makes it possible to identify a PCI device.