The Research Of Procedure-level Dynamic Reconfigurable Computing Technology For High Definition Television’s Application

For the combination of software programming flexibility and hardware efficiency,reconfigurable computing is a balance between software and hardware for intensivecomputing. H.264, a High Definition Television standard, has much bettercompressibility and definition, compared to other High definition Televisionstandards.Nevertheless, its high compressibility is at the cost of large-scale computing,which can be hardly supported by general computers and is too costly to specifichardware. This paper has done some research into Procedure Level reconfigurablecomputing, which is used in H.264video standard. The main works for the paper asfollows:To begin with, Procedure-level dynamic reconfigurable computing is studied,and Procedure-level hardware/software co-design processes are presented from theview of programming model. The works should be finished at the stage of description,and synthesis and executing environment are proposed.Additionally, the H.264codec is partitioned into sub-modules and all of them areinvestigated. Deblocking filter, the main module to decrease the video effectiveness,is the primary researching object. A new filter sequence based-on block is put forward,a pipeline design is given, and suitable RAMs are designed to cut down theintermediate data, data path for strong filter are optimized.Then, the deblocking filter design is analyzed theoretically, and realized inhardware description language Verilog. Simulations are carried out by Modelsimplatform to verify the functions. The result of synthesis proved the design is viableand superior.At last, the design is packaged into IP core, which can be used by other people.