A Study On Deblocking Filter Algotithm And Its Hardware Implementation In H.264

H.264 is the latest generation of the international video encoding standards based on JVT (Joint Video Team) , which is formed by VCEG (ITU-T Video Coding Experts Group) and MPEG (ISO/IEC Moving Picture Experts Group). It is now one of the hot topics in the field of image. As compared with existing standards, H.264 has many new features that contribute to its high performance. Now H.264 has been widely used in digital video communication and storage.The blocking artifacts can occur from block-based processing, such as block-based prediction, motion compensation, transformation, quantization and its inverse process in video stream encoding and decoding system. Therefore, adopting deblocking loop filter can remove these blocking artifacts and achieve much better subjective and objective visual quality and degrade the distortion in the boundaries of blocks. It can also decrease the accumulation errors between frames.There are two aspects discussed in this dissertation: algorithm and hardware implementation. First, with an emphasis on the algorithm of H.264 which is structured of two layers, the concept of the video compression, common video compression standards and their main properties are introduced in this dissertation. And then we describe the deblocking filter principle in detail, the methods to determine the border varying from different levels, which is able to adapt to chip-level, image-level and image block boundary samples. We analyze different boundary filtering process of intensity. Finally we test the filtering algorithm. Improved result can be seen in filtering the effect in case of low bit rate. The image of the border has become smooth, the subjective quality improved. And an improved filtering algorithm also be proposed to facilitate the realization of the hardware.As to hardware implementation, we proposed a deblocking filter hardware circuit based on the proposed optimization algorithm and the filter sequence. According to the function, deblocking filter is divided into five main modules: the top-level control module, parameters and data cache module, parameter calculation module, filter module and output module cache. We describe each module with verilog HDL and simulate them in the Quartus II environment. We synthesize the deblocking filter and analyze the area and power of the entire system. The deblocking filter circuit used here stores the filtering process in the cache, which reduces the access to external memory and the dependence on external memory. An improved filtering sequence is used to reduce the scale.Finally, we summarize the whole research work and prospect the future research.