Drenoc:research And Implementation Of Dynamically Reconfigurable Computing System Based-on Network-on-chip

With the improment of semiconductor manufacturing process and IC design capability, traditional system architecture cannot meet the needs of the billion-transistor area. In case of this situation, mult-core system emerges and has been widely acknowleged. And heterogeneous multi-core including general-purpose processors and specific coprocessors is an important branch of them. Reconfigurable computing technology has the advandage of both processors and ASICs, and is one of the important design technologies of coprocessor. Meanwhile, Network-on-Chip is considered to be the optimum scheme of on-chip interconnection. And reconfigurable computing is proposed to fill the gap between general processors and ASICs. And based-on the sufficient study of Network-on-Chip and reconfigurable computing, this paper proposes and designs a system targert on parallel computing, and verifies the function and performance.The main job of this thesis is as follows:Firstly, propose a system targert on parallel computing and design a FPGA prototype, introduce the design method and process based-on cooperation of software and hardware.Secongly, introduce the design of dynamically reconfigurable system-on-chip in details, and describe the working scheme of stream of context words and data.Finally, verify the function and performance. Based-on the mapping of sequential matrix multiplications, 2-D IDCT and JPEG decoding, the system function and performance are proved.