Architecture Of Reconfigutable Deblocking Filter Based On SIMD Technology

In order to improve visual quality and saving code rate, Most of the discrete cosine transform based video coding standard have introduced a loop filter to remove blocking artifacts. Owing to deblocking filter operation's data-intensive characteristic and requirements of real-time video decoding, the hardware deblocking filtering accelerator has gradually become a research hotspot in recent years.This paper introduces the digital video compression technology, digital video coding standard, MPEG series of standards developed by ISO/IEC Moving Picture Experts Group, series of H.26x developed from the ITU-T standard, Google introduced WebM/VP8 open sourcevideo standards, RealNetwork's RealVideo video encoding format, as well as China with independent intellectual property rights of audio and video coding standard AVS.The second chapter describes the basic framework of video coding standards, including predictive coding, transform coding and entropy coding are three main types of video compression technology. And describes the key technologies in H.264, and AVS standard.The third chapter on the video compression coding standard block effect causes, and to the block effect filter algorithm and two different filters:loop deblocking filter and post filter.The forth chapter describes the characteristics of the deblocking filter algorithm, including fast boundary analysis, filtering to calculate the similarity analysis of the algorithm in two parts, and laid the foundation for multi-standard reconfigurable deblocking filtering VLSI architecture.The fifth chapter describes the deblocking filter based on a SIMD reconfigurable VLSI design, including architecture design, multimedia SIMD Extensions instruction set design, pipelined deblocking filter design.Compared to the traditional hardware accelerators which support single standard for deblocking filtering, designed reconfigurable deblocking filter has the following advantages:Implements a deblocking architecture which filtering algorithm can be reconfigured to support multiple video encoding standards; Adopted SIMD technology, all the filtering data computing parallelly, the hardware can thereby highly regularly structured which is convenient for chip layout; Designed a 6-stage reconfigurable pipeline to enhancing hardware utilization and gaining a high system throughput which reuse of hardware resources and configured into different video standards. A multi-standard accelerator deblocking filter which supports H264, AVS, VP8, RealVideo standards has implemented.The maximum operating clock frequency is 200MHz, it can be used for real-time multi-standard HD video deblocking filtering.