Design And Optimization Of A Hybrid Architecture Of Multi-core Reconfigurable Computing System

With the development of semiconductor and Electronic Design Automation technol-ogy progress, the capacity of chip doubled every 18 months according to Moore’s law, but the amount of computation for applications increased by geometric index. Limited to the device processing technology, only increasing the clock speed of single-core chip is unable to meet requirements of complex computation, a large amount of data, highly real-time of modern application. Under this background, various new computational architectures emerged, the development of a new computational technology matured.The paper designed and optimized Multi-core Reconfigurable Computing System based on FPGA, It can stably run at 100MHz clock frequency. Several floating-point intensive computing applications are performed in the system before and after optimiza-tion. This not only verified the correctness of the original system, and proved the feasi-bility of the optimization strategy. The main work of this paper is as following:1. Summarize the development and research status of reconfigurable computing technology and multi-core technology, and design the reconfigurable computing system model according to the multi-core design direction.2. The paper designed and optimized Reconfigurable Computing Core. Reconfigura-ble Computing Core mainly includes Reconfigurable Computing Array and pipeline. Pipeline mainly performs discrete instruction and control instruction which is not suita-ble for Reconfigurable Computing Array, It enhanced the adaptability of system to algo-rithm, and improved the computational efficiency of system. At the same time, the paper proposed kinds of optimization strategy in the view of their characteristics.3. The paper designed Network on Chip acted as efficient communication architec-ture of multiple computing cores parallel computing, It supports multiple data parallel transmission; Data communication time reduced and computational efficiency is im-proved by optimizing hardware control logic and a reasonable storage space design.4. The paper verified the efficiency and flexibility of prototype system and proved the good effect of optimization strategy by finishing floating-point matrix multiplication algorithm, inverse matrix algorithm, matrix eigenvalue decomposition algorithm, Mo-tion Estimation algorithm in the system before and after optimization.