Research Of Video Decoding Accelerated Method On Reconfigurable Multi-core Processors

With the rapid development of embedded systems, multimedia has put forward higher requirements to embedded systems, such as power, flexibility, cost, and integration, which makes the hardware operation mode based on the ASIC and the software operation mode based on the general purpose processor cannot meet the requirements. Reconfigurable concept is a new computing architecture proposed in this context which is integrated with to the high efficiency of hardware and the flexibility of software. Reconfigurable multi-core processor which is based on "embedded ARM processor+reconfigurable computing cell array" architecture, not only combines the advantages of ASIC and general-purpose processor, but also increases the reconfigurable array of parallel processing computing unit complex operations, and the characteristics become a way to address the diverse needs of multimedia.H.264 video standard, also named MPEG-4 Part X, is raised by the ITU-T Video Coding Experts Group (VCEG) and the Joint ISO/IEC Moving Picture Experts Group (MPEG) coalition. This paper makes full use of the GReP simulation processor which is from the 863 items supported by Beijing Jiaotong University and Tsinghua University to further improve the efficiency of H.264 video codec algorithms. However, due to the limitations of current processor, this paper mines possibility of parallel mapping based on the IDCT inverse transform algorithm and the deblocking filter algorithm both computationally intensive algorithm, and proposes two algorithms in reconfigurable multi-core processor unit of university of parallel processing scheme. The main contents and innovations are as follows:(1) Analysis the standard H.264 video decode algorithms and find suitable algorithm for the reconstruction of multi-core processors to implement parallel mapping algorithm from all the algorithms. According to the compatibility the analysis of reconfigurable hardware and the analysis of core processing unit, the paper proposed algorithm of parallel mapping scheme, according to the rules of mapping is generated corresponding data flow diagram, the reconfiguration of multi-core processor and general purpose processor was conducted to validate the analysis, and compare results of two processors.(2) In this paper, the inverse discrete cosine transform (IDCT) algorithm and deblocking filtering (deblocking) algorithm, analysis of dependence of its internal structure, the division of tasks in different areas of their reconfigurable processor execution proposed corresponding parallelization mapping scheme, verification results show that the algorithm greatly reduces the space complexity and time complexity, in order to achieve a certain acceleration effect.