H.264 Deblocking Filter And Verification On The FPGA

The pixels of picture were divided into many non overlapping blocks for encode, according to H.264,so the image reconstructed may have blocking effect on each block. A filter is applied to each decoded macroblock to reduce blocking distortion. The deblocking filter is applied after the inverse transform in the encoder (before reconstructing and storing the macroblock for future predictions) and after transform in the decoder (before reconstructing and displaying the macroblock). The filter smooth block edges and improves the appearance of decoded frames, and improves the appearance of decoded framesFor each macroblock and each component, vertical edges are filtered first, starting with the edge on the left-hand side of the macroblock, proceeding all the edges till the right-hand side of the macroblock. Afterwards the horizontal edges are filtered, starting with the edge on the top of the macroblock till the bottom of the macroblock. Because the current block edges necessarily reference the neighbour blocks to be filtered, how to store the reference data and array filter order will direct determine chip area, filter rate and reference access frequency to SDRAM. This paper analyses the video encode, considering the correlativity of each block in a macroblock on space. we choose processing unit as blocks but not macroblock, then adjust filtering order of each block, At last we choose a proper filtering order from a macroblock's point of view, to make all the blocks filtered with vertical edges first, and horizontal edges later. So filtering starts with the edge on the left-hand side of a macroblock till the right-hand side, and then starts horizontal edges from the top of a macroblock to the bottom in their geometrical order. The hardware of deblocking filter was designed according to the result studying, in field of filter rate, reduces the number of clock that the filter waits for the filtering data and transfers data, and prepares to reference data from SDRAM, in field of memory, we should use less memory as far as possible to reduce the half filtered data under the premise of a satisfying filtering rate, and cut down the memory about 1/3 to primitive filter structure.The filtering results are completely consistent, from RTL simulation, software process. The result verifying on the FPGA indicates that the structure of hardware...