The Research On SOI LDMOS Phased CCD Array

Since it was proposed by Y.Tarui in1969LDMOS has developed increasingly. LDMOS has a much higher switching speed and cutoff frequency comparing with bipolar device, which was applied in power electronics as a switch because it’s a unipolar device without minority carrier storage effect and the delayed time related to charge storage is much shorter than the counterpart of bipolar device. Meanwhile, LDMOS has a lot of advantages in RF application over bipolar transistor. The transconductance of LDMOS can keep in a high level and it’s a constant in a wide current rang so that LDMOS has a large dynamic range in linear amplification. Simultaneously, it can provide a higher linear gain under a high output power and lower intermodulation distortion. All these advantages are beyond the bipolar transistor.With the continuous development of VLSI technology, the feature size of CMOS CCD has been becoming smaller and smaller. But CCD arrays becoming larger and larger, which leads to large scale CCD array and even ultra large scale CCD array. Therefore, the power driving requirement of CCD array is becoming higher and higher, which requires a strong driving ability of larger current under the given voltage and frequency and a smaller chip area. But it’s rather difficult to meet all these requirements at the same time with a pure CMOS driving circuit. However, SOI LDMOS has a strong driving capability of high power under high voltage and frequency. It’s a good choice as the primary driving stage of CCD array. Moreover the primary driving circuit with SOI LDMOS is compatible in process with standard CMOS and it costs much smaller chip area. As a result, SOI LDMOS is the first choice for power driving of large scale CMOS CCD array.In this paper SOI LDMOS is used under higher voltage and frequency to provide a larger current driving capability instead of pure CMOS circuit for driving of large scale of CCD array. By simulation with Silvaco TCAD and calculation of the driving current CCD needed and their time constants were obtained, base on which the parameters of SOI LDMOS were designed and validated by simulations with Silvaco TCAD. On that basis, the CMOS inverter driving requirement model of loaded SOI LDMOS was found, and then the CMOS inverter driving requirements of SOI LDMOS were calculated by the model.Finally the3-stage CMOS inverter schematic and latout were figured out. All of layouts in this paper were designed by the0.5μm SOI CCD CMOS Process Design Kit.