An Investigation Into Capacitance Characteristics Based On LDMOS And Device Modeling

Advances in semiconductor technology led to the rapid development of integrated circuits, in particular, has made great development in recent years, power IC, the IC market has also increased. Very suitable for high-voltage LDMOS devices used in power integrated circuits, this is because: on the one hand, the gate, source and drain of the high-voltage LDMOS devices in the surface of the device, so that will be conducive to compatibility with other CMOS devices; the other hand, high-pressure LDMOS devices with high breakdown voltage and low-resistance. Bulk silicon LDMOS devices in recent years more and more.Device modeling the electrical properties of devices by model simulation, the device model is a necessary element in the circuit simulation, the simulation results correctly reflect the electrical properties of the device is largely determined by the device model the establishment of good or bad, so the device model is good or bad a direct impact on circuit simulation results. The macro model is not due to the diversity of the high-voltage LDMOS devices, as well as the complexity of device structures in recent years can be used for circuit simulation of device, and the model simulation results are not too satisfactory. Established in this paper can be used in a macro model for SPICE simulation of high voltage devices.First, starting from the static characteristics of the device, With software Tsuprem4, to establish the structural model of the device. Combination of semiconductor theory and2D device simulation software MEDICI meet the premise of the breakdown voltage and conduction current in the design to maximize the pressure characteristics of the device and reduce device on-resistance in repeated in the simulation, the final device to optimize the process parameters. Second, the dynamic characteristics of the devices, through theoretical calculations and software approaches to study the characteristics of the LDMOS capacitance, in particular, the analysis is done a lot of the gate-drain parasitic capacitance and gate-source parasitic capacitance and gate leakage by simulating a variety of structural parameters capacitance effect, theoretical calculations of data and software simulation results compared to some conclusions. These conclusions, in the design of LDMOS, on the one hand, provide a reference to optimize the design of LDMOS structure parameters; the other hand, can also verify the accuracy of the model. Finally, the proposed power LDMOS devices create a macro model, proposed a new equivalent circuit model of the macro, and finally by the MEDICI simulation with SPICE simulation, transient analysis of the macro model and the static IV characteristics, verification of this article the macro model is put forward to meet the requirements of circuit simulation.Through the above work, this paper established a power device LDMOS SPICE macro model, because the establishment of universal, so this method can be used in a variety of high voltage devices and device modeling.