FPGA Design And Implementation Of Image Compression System Based On CAN Bus

The implementation of on-board image compression system requires not only abetter compression performance of coding techniques, but also to achieve requirementslow power and low weight, so the research on real-time image lossless encoder with lowstorage, low power consumption, high reliability, and high-performance has importantsignificance in the field of aerospace study.This paper mainly studies the FPFA design and hardware implementation of imagecompression system based on CAN bus. CAN bus which has a good real-time andanti-electromagnetism interface characteristics, can realize communication betweenon-board image compression system and other nodes. as a communication controlinterface, CAN bus is connected with on-board computer, its monitoring and controlfunction makes the possibility of command interactions between on-board computer andFPGA; because JPEG_LS is a lossless compression algorithm which has lowercomplexity, and is easier for hardware implementation, so JPEG_LS is a core algorithmin image compression module, front-end and back-end interface modules ensure theintegrity of the data path in this paper.This paper first presents a in-depth study of the JPEG_LS image compressionalgorithm and knowledge of CAN bus, followed by a designing of whole imagecompression system and its implementation on FPGA. During the implementation, wefocuses on the CAN control module and JPEG_LS image compression modulehardware implementation, and finally analyze the system performance. Each module ofthe image compression system has been designed and implemented using logic interfacecircuitry on Xilinx FPGA. The test results of whole system show that the systemstability, high performance and good reliability have reached the establishedrequirements.