Research Of High-Dynamic Range Image Compression Algorithm Based On FPGA

High dynamic range image(High-dynamic range image)is referred to as HDRI.Compared to ordinary images,it contained more dynamic range information and more details,also the hierarchy of the image is more distinct,which can fully display the real scenes.Nowadays,high dynamic image technology has been widely used in automobile vision,monitoring security,especially satellite remote sensing,in which high image quality is need.However,to store higher dynamic range,the single pixel of high dynamic range image occupies a large storage space,which makes the image transmission and display technology hard to meet the requirements.Traditional Digital Image display system can only display 8bit image,while the single pixel of high dynamic image can reach up to 32 bit.Direct quantization with linear compression method is difficult to meet the requirements of high demand occasions.For a better display,the HDR image is typically compressed with a specific dynamic range compression algorithm.At present,most high dynamic image compression algorithms need to run on the CPU based PC platform,which cannot adapt to aerospace or security monitoring,in which low power consumption,high portability and real-time process are need.To solve these problem,this design used FPGA device to design a special HDR image compression hardware architecture.Under the condition that the architecture can satisfy the compression demand,it can make up for the shortage of software compression algorithm.This paper designed a special hardware architecture based on TPEM(tone-preserving Entropy maximization)compression algorithm,which used the VERILOG-HDL hardware circuit design language and was combined with the idea of pipeline design.This architecture adopts the methods of look-up table,approximate calculation and storage mapping to accelerate the TPEM algorithm in aspects of operation,storage and parallelism,which made up the disadvantage of low processing speed and high-power consumption.In addition,this paper also induced a memory map structure based on RAM,which was used to store the intermediate results during the operation of the algorithm.It solved the problem of the low ability of single RAM,the data conflict when reading multiple RAMs and two-dimensional matrix storage mapping,which greatly improved the parallelism of the algorithm.also,this paper developed a verification system with the VIRTEX-6 series FPGA.This system included the USB2.0,JTAC and other data transmission interfaces and an upper computer system which can control and display the system.Finally,in this paper,the results are compared and analyzed in several aspects.The results showed that this architecture have a great ability to do the HDRI compression,at the same time,effectively reduced the power consumption and increased the processing speed.