Based On 40 Nm Process Chip Physical Design Research

As the semiconductor technology progress with Moore’s Law, the new process technology brings great advantage in power consumption, chip area and performance. However, some problem like interconnect delay, crosstalk noise, process variation and reliability also brings huge challenges to physical design. It is worthy that studying and improving the physical design flow to improve design quality and chip reliability.The current physical design flow is introducted firstly, and then the paper study and analysys the physical design challenges in the40nm process. Some suggestion, focoused on power mesh, place, route, and Timing Evolves etc, is proposed to improve the quality of result based on40nm process. At the same time, the variances of physical design between40nm and65nm or above are also pointed out.With the background of the mobile communication base stations application, The physical design of one block of a commercial communications chip base on TSMC40nm process is implemented. Which is a SRAM memory block with capacity of38,400*1024bits, and it has the feature of high speed, high-throughput and low power consumption. The block’s speed is up to370MHz with2.7ns clock period, including162macro,600,000standard cells, corresponding to2million NAND gates. There are5major design phase, Floorplan and power planning, placement, clock tree synthesis, routing and optimization, and static timing analysis and signal integrity analysis. The block layout core size is3576.6um*5659.2um, tradeoff by the power, area etc. In the place/route phase, with placement utilization of60%, a good quality of result is acheived, multi-Vt liberaries are used to descrease the leakage power. Multiple methods are used to fix the setup/hold timing and crosstalk violation. In addition, The routing congestion, power optimization and clock tree synthesis is studied with theoretical analysis and Contrast test, and get some helpful conlusion to physical design.