Information Security Chip Low-power Back-end Design Research

With the development of information technology, information security becomes more and more important. As a result, the security requirement of information technology is becoming higher. Now DES algorithm and AES algorithm can’t satisfy with application requirement, so it’s urgent to provide a new security algorithm. From2007, the National Institute of Standards and Technology calls for a new round Hash algorithm. The new SHA3candidates improve not only iteration structure, but also compression function, which makes SHA3algorithm more secure. But as information security chip used in handheld devices and micro-devices widely, power consumption has increasingly become a bottleneck restricting the development of chip. How to reduce the power consumption of chip system is a vital problem of chip development and application.This paper focuses on one SHA3candidate, BLAKE. We adapt hardware acceleration to make the SHA3instruction execute quickly. And to reduce the power consumption of chip system, we adapt clock-gating, Multi-Vth, Multi-VDD and power-gating technology in the backend flow.Firstly, the paper analyzes the sources of chip power. According to the factors affecting dynamic power and static power, we discuss the feasibility of reducing dynamic power and static power in the front-end design and back-end design.Then, for the hardware accelerated ASIP chip, we perform structure partition and low-power backend design. We adapt synopsys low-power flow in the back-end design. In this flow, we introduce the detail of special cells and create UPF file. Then we analyze and compare the timing and power of the final layout.At last, the paper summarizes the Multi-VDD and power-gating technology. Based on power-gating, we discuss DVFS and AVS technology, and design the architecture of DVFS and AVS, which points out the deficiencies to improve and advance the new research direction and contents in the future.