Font Size: a A A

Research Of High-Robustness ESD Protection Of High-Voltage HVNMOS Device

Posted on:2013-06-14Degree:MasterType:Thesis
Country:ChinaCandidate:J ZouFull Text:PDF
GTID:2248330395486294Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
The reliability of integrated circuits to heavily dependent on the performance of electrostatic discharge protection circuit.For deep-submicron integrated circuit design, the design of effective ESD protection circuit has becomes particularly significant.In integrated circuit design, in order to protect the chip from being electrostatic damage, ensure the chip works, need to apply technology of antistatic discharge damage, design a special ESD protection devices or circuits, to minimize damage to the electronic devices from electrostatic.Manufacturing and testing of integrated circuits and semiconductor devices, to a large extent, depend on the precision of the device. And micro-electronics testing needs of various loss items are expensive, with the help of software simulation and analysis device, can quickly and accurately get various properties of the device, so as to reduce the cost of research and development.This paper uses the MEDICI device simulation software for high-voltage NMOS device and SCR ESD simulation and analysis of the performance, and uses constant-current transmission line pulse (TLP) testing method on the device for an electrical pressure testing and analysis.On this basis, using the circuit simulation software Cadence, based on0.6umCMOS techniques, using the human body model (HBM) and machine model (MM) on ESD model for simulation of the circuit for high-voltage NMOS device to high voltage I/O pins and SCR and power-rail ESD clamp circuit design and layout design.After analyzing the characteristic of the ESD performance device, layout areas and factors such as reliability, etc. Optionally using two diodes and resistors to make up a high voltage SCR structure (ESD pressure4kV), meanwhile series two isolated PMOS devices to clamp voltage. This circuit should control4kV HBM ESD voltage of the power rail peak voltage to4V or under4V.Due to the experiment conditions, didn’t do the physical test validation.And research on the robustness of ESD protection devices do not go far enough, which is to continue to work hard in the future.
Keywords/Search Tags:ESD protection, SCR, HV NMOS, robustness
PDF Full Text Request
Related items