Research And Design Of Novel Strained Ge NMOS With Stress Gate

As time went on, Moore's law, which is over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years, has been challenged all the time. However, with the decrease in practical size and characteristic dimensions are in namometers, methods to reduce in scale is more and more restricted by the physical condition and technology based on the increase of original silicon CMOS devices.Firstly, in this paper, the key physical parameters, such as the effective mass of the strain Ge, the variation of the stress intensity, the crystal surface, and the mechanism of the strain Ge and the mechanism of the stress of the MOS Ge device have been studied. The interface characteristics of strained Ge MOS and the mechanism of interface state generation and grid drain motor has been analyzed.Secondly, based on the above research, this paper proposes a new structure of strained Ge NMOS formed by a conductive channel, which solves the problem of low activation rate and Ge type P electron mobility in Ge effectively. In order to obtain a higher device current switch, the structure of the GOI Ge NMOS is further proposed;Thirdly, the influence of device's parameters such as channel length, gate angle and depth on the threshold voltage, ION and switch ratio of device has been studied. The simulation results indicated that the gate oxide layer should use high-K material, and the high work function gate metal should be used to obtain larger device switch ratio. When the gate slot angle is less than 80°, the IOFF is large.Finally, the strained Ge CMOS has been proposed. The simulation results show that the high noise tolerance is 0.933 V and the low noise margin is 0.973 V with the output swing is 2V.