Research On Gigabit Transceiver Of Wideband Intergrated Digital Optical Synchronous Network

Network communication is one of the fastest growing areas, and it is closely relatedto people’s life and work, in order to meet the real-time network and business growthrequirements, and can be transmitted in a network of different businesses, different datatypes, different data rate and different connection signaling, a network named WidebandIntegrated Digital Optical Synchronous Network (WIDOSNet) was designed, whichuses the SDH, optical fiber communication, SOPC technology. It transmits the specifieddata at a fixed time slot, and changes data exchange into data option by usingdistributed processing model to achieve the separation of transmission and business.With the rapid expansion of information, high-speed data transmission is being akey consideration of the next generation network (NGN). In network terminal, highspeed serial communication has been replacing the traditional parallel bus interfacetechnology. WIDOSNet is a high-speed communication data rate network, so we chosethe high-speed serial interface in data transmission solutions.The transmission of downstream data from concentrator to the network node ofWIDOSNet was implemented by FPGA SERDES, and the high-speed serialtransceiver’s internal structure and transmission mode was detailed in this paper；TheSERDES was configured and data generation module, reset module are designedaccording to the agreement; and a CAM was designed for the network node to receivesthe data and determine the data type in high speed. Some parts of hardware circuitswere also described to prove the correctness of the design.Finally, this paper makes a summary and points out some improvements. Themodules of this paper are designed by Altera’s Quartus II and Mentor’s Modelsimsimulation software.