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Research And Logic Design Of Video Cascade Splicer Based On FPGA

Posted on:2022-08-14Degree:MasterType:Thesis
Country:ChinaCandidate:W P ShiFull Text:PDF
GTID:2518306551453654Subject:Master of Engineering
Abstract/Summary:PDF Full Text Request
At present,large-screen splicing devices have been widely used in various scenarios,such as exhibitions,news,stations,traffic and military command.This paper analyzes the current status,application scenarios and development trends of large-screen splicer at home and abroad,and establishes the main research content of this thesis based on the performance problems of current large-screen splicer.In the video transmission capacity,resource utilization efficiency,etc.,this paper analyzes key technologies such as data transmission bandwidth,scaling efficiency,and cache bandwidth utilization between the splicer's service boards,and proposes a logic optimization design scheme based on FPGA platform.Compared with the traditional large-screen splicer,this article focuses on the design of video image cross-board cascade,DDR access bandwidth utilization,zoom scheduling,and image splicing mechanism.The main contents are as follows: 1)Design an efficient Video image cascading transmission protocol,based on the 3.125 Gbps high-speed SERDES to achieve the cascade of each business board,which can effectively improve the data transmission capacity between each business board,and realize the flexible upload and download of video data;2)Design a DDR cache access arbitration mechanism,for application scenarios with a large number of video image channels,this mechanism can effectively increase the DDR bandwidth utilization rate,and a more reasonable stitching write back method is designed to reduce the system's access to DDR and the complexity of the design,it saves resource usage and reduces system power consumption;3)A more optimal scaling scheduling mechanism is designed,which changes the traditional design of a certain output channel exclusive of a scaling resource,schedules all scaling resources in a single business board as a whole,avoid waste caused by uneven utilization of scarce resources,thereby improving the overall scaling capability.After verification and test,the bandwidth of cascade transmission can reach 37.5Gbps,and the service boards can be cascaded flexibly,the efficiency of scaling and splicing has been optimized,and the product performance has also been significantly improved.
Keywords/Search Tags:Splicing Controller, Scale, SERDES, FPGA, DDR
PDF Full Text Request
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