Research On Interconnect Model Considering Process Variations

As the process technology of integrated circuits has reached to or surpassed deep submicron-scale feature sizes, the scale and complexity of integrated circuits are increased. The traditional device-centric design methods can not meet the requirements of modern integrated circuits design methods. Especially, when process technology of integrated circuits goes beyond 0.18μm, interconnection has become the crucial factor of IC function and performance instead of device. Research on interconnection-centric design methods has been an important direction of modern VLSI design. Building interconnect model is a key work of interconnection-centric design methods.At the same time, shrinking dimensions and increasing aspect ratios are more and more influenced by process details leading to deviations from ideal interconnect shapes. Even process variations have threatened timing design of high performance integrated circuits, therefore building interconnect model considering process variations is an important subject.This paper embarks on VLSI design development researches traditional interconnect model and the impact of interconnects by process variations, develops several interconnect models considering process variations. Main contributions of the paper include:1. This paper summarizes the features and shortcomings of existing interconnect analysis. This paper clarifies why traditional device-centric design methods can not meet the requirements of modern integrated circuits design methods, analyzes the origins of process variations and the impact of process variations on interconnect, and summarizes interconnection-centric design methods. On this basis, this paper explains how to add process fluctuations to interconnection-centric design flow, and develops an interconnection-centric design method taking process variations into account.2. This paper summarizes the basis of developing interconnect models. This paper analyzed mainstream modeling methods of interconnects including time domain analysis method, transform domain analysis method, mixed analysis method and systematic analysis method etc. And this paper also gives mainstream interconnect delay models, including classic RC interconnect delay model—Elmore delay model, various kinds of RLC interconnect delay models which are modified by Elmore delay model; Analyzes mainstream modeling methods of crosstalk noise, such as lumped parameter model, complex frequency domain analysis of crosstalk in in the end. Furthermore, the mainstream extraction technologies of interconnect parasitic parameters are also summarized and analyzed in this dissertation.3. This paper develops an extreme value estimation of interconnect delay. As one of important interconnects modeling contents, extreme value estimation of RLC interconnect delay effected by process variations is presented in this paper. The method solves the problem of extreme value estimation of interconnect delay under the influence of process variations applying static timing analysis (STA). And the method takes the impact of parasitic inductance into account, which the traditional methods of extreme value analysis can not be competent.4. This paper develops two statistical interconnect delay models. As a thermal issue of interconnect delay model effected by process variations, two statistical interconnect delay models for statistical static timing analysis (SSTA) are presented in this paper. One is based on RC delay model, the other is based on RLC delay model. The statistical model based on RC delay uses optimized quadratic fitting. Delay and slew are expressed directly as functions of interconnect geometric parameters. The proposed strategy is more accurate than former models using linear fitting, and has higher computational efficiency than that using normal quadratic fitting. Comparing to Hspice-based Monte Carlo simulation in the experiment, the proposed method is twenty times faster than traditional method, and also keeps nearly the same accuracy as traditional methods. Typically, distribution characteristics of delay and slew are improved remarkably; The statistical model based on RLC delay combines the first two moments of impulse response and probability density functions (PDF) of Weibull distribution, and considers the effect of interconnect parasitic inductance. In order to get the rapid calculation, physical parameters affected by process variations directly express by shape parameter and scale parameter of Weibull distribution. All the experiments show that the proposed model has better accuracy than other models. Comparing to Hspice-based Monte Carlo analysis of HSPICE, the error of mean and the error of the average deviation in Monte Carlo analysis are less than 2.02%. The method has higher efficiency.5. This paper develops an interconnect crosstalk noise model. For the development of integrated circuit technology, the line space decreases and the aspect ratio (A/R) of interconnects increased continuously, crosstalk noise has become an important factor in performance of interconnects. This paper summarizes the reasons of crosstalk noise of interconnect and the impacts on VLSI design. Based on above reasons, a statistical model of interconnect crosstalk noise is proposed in this paper. The coupled RLC interconnects model with load capacitances and distributed parameters is based on transmission line theory. The model not only takes the load capacitances into account, but also is a distributed parameter model, which is different from the traditional lumped parameter model, can get the voltage and current of arbitrary point in coupled lines. Experimental results show that comparing to Hspice-based Monte Carlo analysis of HSPICE, the errors of models with or without the impact of process variations are less than 5%. Due to the application of the fast numerical inversion of Laplace transforms, the model has very good performance.