Statistical Modeling Of Low Voltage Standard Cell Delay

In recent years,with the continuous development of the integrated circuit industry and the urgent need for low power consumption,the shrinking feature size and the lower operating voltage have become effective ways to achieve demand.However,due to the shrinking of feature size and the drop of the voltage,the standard cell library is usually introduced with a large amount of timing margin,which deteriorates the performance of the circuit seriously.Although the statistical static timing analysis can reduce the timing margin,it still faces various challenges.Under the low voltage scenarios,the existed model can not accurately characterize the non-gaussian feature which results in the loss of model accuracy.When the model is applied to the circuits,the errors of the circuits are aggravated and the credibility of the timing results is reduced.The purpose of this paper is to establish a accurate statistical model of low-voltage standard cells' delay.Considering the cell delay obeys the logarithmic normal distribution under the near-threshold voltage so the logarithmic operation is conducted and the cell delay is divided into delay mean and delay variation.The delay mean is mainly affected by operation conditions and the delay variation mainly considers the influence of process variations.And the rise edge and the fall edge are studied separately.Therefore,the multiple adaptive regression splines(MARS)is used to accurately characterize the relationship between the delay mean and operation conditions.Then in terms of the modeling of delay variation,the third-order model is used to characterize the relationship between delay variation and process variations.Meanwhile,due to the consideration of the speed of modeling,the MARS model is used to speed up the process of the delay variation modeling in order to avoid repeating simulation.In this paper,the SMIC 28 nm process library is used to verify the accuracy of the lowvoltage cell delay model.Under the 0.45 V voltage scenario,the average error of mean is 0.565% and the standard deviation error is 1.294% compared with the results of Monte Carlo analyses.Meanwhile,the model proposed in this paper is applied to ISCAS85 benchmark circuits such as C17,C499,C6288 and so on.The average error of the mean and the standard deviation compared to Monte Carlo results are 3.112%and 10.126%.The experimental results show that the cell delay model proposed in this paper has high accuracy under low voltage and can be applied to path timing analysis.