Analysis Of Interconnect Signal Integrity Based On Process Fluctuations

With the rapid development of technology, very large scale integrated circuits manufacturing process technologies going into the deep submicron regime, rapidly decreasing minimum feature size bring to the forefront new physical issues such as delay and crosstalk. So the impact of process fluctuations on performance has become extremely critical in IC design. To effectively analyze impact of process fluctuations on interconnect performance, the impact of interconnect process fluctuations on the interconnect delay and crosstalk noise in VLSI is studied and discussed in the thesis. The approximate function relationships are obtained by analyzing the impact of interconnect geometric parameters fluctuation on the interconnect parasitic parameters. The statistical RC interconnect delay model, RLC interconnect delay model and crosstalk noise model are successfully proposed and built respectively. The mathematical expressions of mean and standard deviation of interconnect delay and crosstalk noise can be obtained by using the proposed models. The time of calculation is greatly shortened with a good calculating precision using the obtained method compared with the widely used Monte Carlo simulations. It is proved that they have high efficiency and are accurate enough, so our models are more practical.