Font Size: a A A

Design And Optimization Of H.264Deblocking Filter Based On FPGA

Posted on:2013-05-30Degree:MasterType:Thesis
Country:ChinaCandidate:X F ZhangFull Text:PDF
GTID:2248330395456154Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
DCT transform, quantization and motion compensation based on blocks are usedin H.264to compress video data. This kind of video compression techniqueunavoidably brings blocking artificial edges, which will degrade image quality andblock transmitting under low coding ratio. To improve image quality, a deblockingfilter is applied in H.264. As an essential part in H.264, the deblocking filter plays animportant role in removing annoying blocking distortion. In this thesis, we focus on thehardware design and implementation of the module.This thesis gives an outline of video encoding and FPGA technologies, analyzesthe principle of H.264deblocking filter, which is the theoretical basis of this thesis.And then proposes an optimized deblocking filter without changing the filter results:the reference data are stored in registers in order to speed up the filter and reduce theaccess frequency to SDRAM; considering the correlativity of each4x4block in amacroblock on space, a proper filter order is applied; we also propose a new design ofdata input and ouput structure, the mode of input data is more adapt to the filter order,there are9modes of output data,which are good for outputting the data as soon aspossible; and then a parallel computing architecture is proposed to speed up the filter.Based on the above design ideas, the internal structure and the level of division of thewhole system are given, the detailed description and implementation of the deblockingfilter are made, and the whole system is realized by verilog hardware descriptionlanguage.At last, the final test of the system is done on modelsim, using PLI technology. Wealso established a reference sofeware model, which is separated from X.264. Wechoose Virtex5-XC5VLX330T as hard device. The synthesis results by ISE XST aregiven:7%registers and13%LUT are used,104MHz frequency. Compared with theexisting design the filter speed has been improved, filtering a whole microblock onlyneeds136cycles.Simulation results show that the deblocking filter has achieved theexpected demand.
Keywords/Search Tags:H.264, FPGA, Deblocking Filter
PDF Full Text Request
Related items