Research And Hardware Implement Of Deblocking Filter In H.264

As the standard of video compression designed for IP and wireless environment, H.264 has been widely accepted by its higher compression ratio and better image quality. H.264 absorbs several key technologies, including intra prediction,4×4 integer transform, multiple reference frame motion estimation, context-based adaptive binary arithmetic coding to keep its high performance on the compression area, compared to the other standards exited. But these technologies can also bring blocking artificial to the decoded pictures. H.264 introduces a deblocking filter in its codec to remove blocking artificial.Followed by the algorithms of deblocking filter in H.264, a FPGA based architecture is designed. Several improvements have be introduced to this design, such as modified the filter order of block boundary and cut off the filter process to several sub-process parts. The modigy of filter order can multi-use the filter data and reduce the clock cycles used for memory read/write; the cut off to the filter process is good to pipelined the whole filter operation. At last, the EDA tools are used to test the filter results and do some simulation work of the design.