Design Of Entropy Coding And Deblocking Filter In H.264 Based On FPGA

H.264 is the newest generation video compression encoding standard developed jointly by ITU-T Video Coding Expert Group (VCEG) and ISO/IEC Moving Pictures Expert Group (MPEG) Joint Video Team (JVT). The new standard introduces some advanced video encoding technology, including multi-mode inter estimation, 1/4 fractional pixel motion estimation, entropy coding based on the context, integer DCT transform, deblocking filter, etc, which has the merits of high compression ratio, network friendliness and so on. It can afford the satisfying performance for gaining high quality video in low-code rate transmission, and it has been widely used in many aspects of video development.Along with the development of EDA technology and the accelerative growth of high-performance scale programmable logic device, SOPC technology combining with advantages of SOC, PLD and FPGA has been widely used in many fields of embedded development. Based on deeply studying H.264 encoding and decoding algorithm, the paper has performed the design for H.264 video encoding and decoding system by using DE2 development board developed by Altera Corporation. FPGA implementation of CAVLC entropy encoder, inverse quantization inverse transformation and deblocking filter is emphatically studied in the paper. The paper mainly includes the following several aspects:1) CAVLC performs coding data compression on the basis of distribution characteristic of residual being processed by transform&quantization and reduces redundant information further. Compared with CABAC, its complexity is low and has a relatively low impact on encoding time. Through the analysis of CAVLC encoding algorithm, the paper summarizes CAVLC encoding flow, and then has completed hardware circuit design of CAVLC entropy encoder. It significantly improves encoding efficiency via three-stage pipeline operation.Simulation and FPGA verification has been done for the whole CAVLC entropy encoder. The verification result shows that the encoding system clock can reach more than 100MHZ. 2) According to algorithm flow and implementation structure of IQIT, hardware circuit design of inverse quantization of residual coefficient, inverse integer DCT transformation and inverse Hadamard and inverse quantization of DCT transform coefficients's direct coefficients.on this basis, hardware circuit design of IQIT module for mb residual outputed by CAVLC entropy decoding, and simunlation has been done for it's entirety.3) Through the analysis of deblocking filter algorithm, hardware implemented architecture of deblocking filter is proposed for H.264/AVC. It increases deblocking filtering processing speed by using five-stage pipeline design and improves filtering order to meet the need of pipeline processing. Three-layer state machine is adopted to control filtering process in the filter, and it effectively decreases the complexity of hardware design. Through properly increasing the usage of the internal SRAM, it improves system processing speed and data throughput.Simulation and FPGA verification have been done for the whole deblocking filter. The verification results shows that it can meet 25 frame/s real-time filtering for CIF size image.In brief, the due design goal has been achieved in the paper, and it can provide definite reference for application development of H.264.